Reduced activation temperature of B impurities in Si(001) epitaxial layers grown by sputter epitaxy using B-doped Si(001) target compared with Si(111) target（2025-03） [DOI]
Hole-tunneling Si0.82Ge0.18/Si triple-barrier resonant tunneling diodes with high peak current of 297 kA/cm2 fabricated by sputter epitaxy（2024-02）
Sn distribution in Ge/GeSn heterostructures formed by sputter epitaxy method（2022-12-18）
Increasing the critical thickness of SiGe layers on Si substrates using sputter epitaxy method（2022-09-29）
Direct Growth of Patterned Ge on Insulators Using Graphene（2021-06-18）
Evaluation of crystallinity of lattice-matched Ge/GeSiSn heterostructure by Raman spectroscopy（2021-05-31）
Simple annealing process for producing unique one-dimensional fullerene crystal named fullerene finned-micropillar（2020-11-06）
Hole-tunneling Si0.82Ge0.18/Si asymmetric-double-quantum-well resonant tunneling diode with high resonance current and suppressed thermionic emission（2020-07-27） [DOI][Web of Scientce]
Increase in Current Density at Metal/GeO2/n-Ge Structure by Using Laminated Electrode（2019-11-19）
Effects of Low-Temperature GeSn Buffer Layers on Sn Surface Segregation During GeSn Epitaxial Growth（2019-11-14）
Crystallinity control of SiC grown on Si by sputtering method（2017-04） [DOI][Web of Scientce]
p-Cu2O/SiOx/n-SiC/n-Si memory diode fabricated with room-temperature-sputtered n-SiC and SiOx（2016-12） [DOI][Web of Scientce]
Control of surface flatness of Ge layers directly grown on Si (001) substrates by DC sputter epitaxy method（2015-10） [DOI][Web of Scientce]
Low-temperature fabrication technologies of Si solar cell by sputter epitaxy method（2015-08） [DOI][Web of Scientce]
Formation of GeSn layers on Si (001) substrates at high growth temperature and high deposition rate by sputter epitaxy method（2015-06） [DOI][Web of Scientce]
Investigation of Sn surface segregation during GeSn epitaxial growth by Auger electron spectroscopy and energy dispersive x-ray spectroscopy（2015-02） [DOI][Web of Scientce]
p-Cu2O/SiCxOy/n-SiC/n-Si memory diode having resistive nonvolatile memory and rectifying behaviors（2014-07） [DOI][Web of Scientce]
Planar electron-tunneling Si/Si0.7Ge0.3 triple-barrier resonant tunneling diode formed on undoped strain-relaxed buffer with flat surface（2014-03） [DOI][Web of Scientce]
Effects of DC Sputtering Conditions on Formation of Ge Layers on Si Substrates by Sputter Epitaxy method（2014） [Web of Scientce]
Effects of boron dopants of Si (001) substrates on formation of Ge layers by sputter epitaxy method（2013-10-21） [DOI]
PN-Diode P-Oxide-Semiconductor/N-SiC/N-Si Resistive Nonvolatile Memory for Cross-Point Memory Array（2013） [DOI][Web of Scientce]
Layered Structures of Interfacial Water and Their Effects on Raman Spectra in Graphene-on-Sapphire Systems（2012-05） [DOI][Web of Scientce]
Evolution of step morphology on vicinal sapphire (1-102) surfaces accompanied with self-assembly of comb-shaped chemical domains（2012-05） [DOI][Web of Scientce]
Effects of Surface Chemistry of Substrates on Raman Spectra in Graphene（2012-02） [DOI][Web of Scientce]
Graphene etching controlled by atomic structures on the substrate surface（2012-02） [DOI][Web of Scientce]
Fabrication of Three-Dimensional Porous Alumina Microstructures Using Imprinting Method（2012） [DOI][Web of Scientce]
Control of Graphene Etching by Atomic Structures of the Supporting Substrate Surfaces（2011-05） [DOI][Web of Scientce]
'Graphene-on-insulator' fabricated on atomically controlled solid surfaces（2010-09） [DOI][Web of Scientce]
Control of the spatial distribution of porous alumina micro-domes formed during anodic oxidation（2009-08） [DOI][Web of Scientce]
Morphology of Graphene on Step-Controlled Sapphire Surfaces（2009-07） [DOI][Web of Scientce]
Observation of Three Dimensional Micro-Scaled Structures Buries in Porous Alumia Layers Fabricated by Anodic Oxidation（2008） [DOI]
